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We anticipate that this process will expand to include others in a Secure Device Onboard technical steering committee comprised of community contributors and ecosystem stakeholders.","type":"text"}]},{"type":"paragraph","content":[{"text":"Tom Barnes (Intel) is the project manager for Secure Device Onboard where he is responsible for planning and processes. He has previously contributed to the LF Hyperledger Sawtooth, Avalon, and Private Data Objects projects. We anticipate that Tom will be an initial maintainer for the Secure Device Onboard project.","type":"text"}]},{"type":"paragraph","content":[{"text":"Saurabh Dadu (Intel) is the chief architect for Secure Device Onboard. He is responsible for translating the feature roadmap into technical requirements and architectural specifications, for maintenance of the Secure Device Onboard protocol specification, and for the overall security architecture of Secure Device Onboard. We anticipate that he will continue in this role as part of the Secure Device Onboard Technical Steering Committee.","type":"text"}]},{"type":"paragraph","content":[{"text":"John Easterday (Intel) and Tushar Ranjan Behera (Intel) are the technical leads for the Secure Device Onboard project. They are responsible for software development as well as for oversite of devops and validation activities. We anticipate that they will be initial maintainers for the Secure Device Onboard project, with responsibility for ensuring contributions are properly and promptly reviewed and approved, and that they will eventually be joined by other contributors as the community of contributors grows.","type":"text"}]},{"type":"paragraph","content":[{"text":"Richard Kerslake: Secure Device Onboard – Director. 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As the community of contributors grows, we anticipate that the governance model will evolve into a core team/sub-team model similar to the one used by the Rust project as described here: ","type":"text"},{"text":"https://github.com/rust-lang/rfcs/blob/master/text/1068-rust-governance.md","type":"text","marks":[{"type":"link","attrs":{"href":"https://github.com/rust-lang/rfcs/blob/master/text/1068-rust-governance.md"}}]},{"text":".","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Preferred maturity level (see stages ","type":"text"},{"text":"here","type":"text","marks":[{"type":"link","attrs":{"href":"http://lf-lfedge.atlassian.net/wiki/display/LE/Project+Stages%3A+Definitions+and+Expectations"}}]},{"text":")","type":"text"}]}]},{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"Secure Device Onboard is applying for Stage 1: At Large Projects","type":"text"}]}]}]},{"type":"tableRow","content":[{"type":"tableCell","attrs":{"colspan":1,"rowspan":1},"content":[{"type":"paragraph","content":[{"text":"For Projects applying at the Growth (Phase 2) or Impact Stage (Phase 3), please outline how your project successfully meets/exceeds the requirements as defined under each category. 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